1. Field of the Invention
The present invention relates to semiconductor device and a fabricating method of same, and more particularly, to a semiconductor device and a fabricating method of same having a reduced step difference between a DRAM cell region and a logic device region.
2. Discussion of the Related Art
As integration and density of semiconductor devices increases and memory cell area decreases, increasing the density of capacitors having a high charge storage capacity becomes increasingly important. In order to increase the capacitance of each capacitor, a surface area of a dielectric is increased by forming a capacitor having either a stacked structure or a three-dimensional trench.
A device having both a DRAM cell and a logic device integrated on a single chip is formed by combining a known process of fabrication of the DRAM cell with a known process of fabrication of the logic device.
FIG. 1 shows a cross-sectional view of a conventional semiconductor device. A field oxide film 13 defining an active area is formed on a p-type semiconductor substrate 11. A transistor having a gate 19 and source/drain junctions 15, 17 doped heavily with N-type impurities is formed on an active area on the substrate 11. The gate 19 is surrounded by an insulating layer 21 and is isolated from the substrate 11.
A bit line 23 is formed in contact with the drain junction 17. The insulating layer 21, an insulating interlayer 24 on the bit line 23, a planarized layer 25, and an etch-stop layer 27 are formed sequentially, and then a contact hole 29 exposing the source junction 15 is formed by etching the etch-stop layer 27, the planarized layer 25 and the insulating interlayer 24. A storage electrode 31 of a capacitor is formed with doped polycrystalline silicon, and a lower portion of the storage electrode 31 is in contact with the source junction 15. The storage electrode 31 fills the contact hole 29, and an upper portion of the storage electrode 31 having a crown shape is formed on the etch-stop layer 27.
A dielectric film 37 including oxide or nitride/oxide is formed on a surface the storage electrode 31, and then a plate electrode 39 is formed on the dielectric film 37.
FIGS. 2A to 2D show cross-sectional views of a conventional process for fabricating the semiconductor device. Referring to FIG. 2A, a transistor is formed on the active area defined by the field oxide film 13 on the P-type semiconductor substrate 11. The transistor includes the gate 19 surrounded by an insulating layer 21 and isolated from the substrate 11, and source/drain junctions 15, 17. The bit line 23 is formed in contact with the drain junction 17. The insulating interlayer 24 including oxide is formed over a surface of the entire structure, and the planarized layer 25 is formed on the interlayer 24 by depositing a material having good flow characteristics, such as, for example, PSG (Phospho Silicate Glass), BSG (Boro Silicate Glass) and BPSG (Boro Phospho Silicate Glass).
An etch-stop layer 27 is formed by depositing a material having a different etch selectivity from the planarized layer 25 on the planarized layer 25. The contact hole 29 is formed using photolithography to expose the source junction 15 by removing portions of the etch-stop layer 27, the planarized layer 25 and the insulating interlayer 24.
Referring to FIG. 2B, the first polycrystalline silicon layer 31 doped with impurities is formed on the etch-stop layer 27 by CVD (chemical vapor deposition), filling up the contact hole 29 and in contact with the source junction 15. A mask pattern 33 is defined by leaving a corresponding portion on the contact hole 29 after an oxide layer has been deposited on the first polycrystalline layer 31. Furthermore, a sidewall spacer 35 is formed on lateral sides of the mask pattern 33 by etching back a nitride layer which has been deposited on both surfaces of the polycrystalline layer 31 and an exposed surface of the mask pattern 33.
Referring to FIG. 2C, the first polycrystalline silicon layer 31 is patterned into a pillar shape by etching using the mask pattern 33 and the sidewall spacers 35, exposing the etch-stop layer 27. The remaining portion of the first polycrystalline silicon layer 31 is exposed by removing the mask pattern 33. Using the sidewall spacers 35 as a mask, the exposed part of the polycrystalline silicon layer 31 is etched into a shape of a cylinder or a crown, and the etch-stop layer 27 prevents the planarized layer 25 from being removed. The sidewall spacers 35 remaining on the first polycrystalline silicon layer 31 is then removed and at the same time the exposed portion of the etch-stop layer 27 is removed, and the remaining portion of the first polycrystalline silicon layer 31 becomes the storage electrode 31.
Referring to FIG. 2D, a dielectric film 37 is formed on the surface of the storage electrode 31 (the first polycrystalline silicon layer 31). The dielectric film 37 includes one of oxide, oxide/nitride, Ta2O5, PZT (Pb(Zr Ti)O3) and BST ((Ba Sr)TiO3). A second polycrystalline silicon layer 39 doped with impurities is formed on the dielectric film 37 to form the plate electrode 39.
The conventional semiconductor device fabricated by the above method has a Diagonal Capacitor On Bit Line structure, increasing the capacitance due to the increased area of the capacitor by forming the bit line 23 before the formation of the capacitor and also simplifying the process by decreasing an aspect ratio of the contact hole 29 which causes difficulty in contacting the bit line 23.
However, as the DRAM cell having the Diagonal Capacitor On Bit Line structure and the logic device are formed on a single chip using the conventional method, the process gets complicated.
Moreover, since the large step difference between the DRAM cell area and the logic device area causes poor resolution in the process of forming a conductive line, a fine photoresist pattern is hard to define.
is Accordingly, the present invention is directed to a semiconductor device and a fabricating method thereof that substantially obviates one or more of the problems and limitations of the related art.
One object of the present invention is to provide a semiconductor device which decreases the step difference between a DRAM cell area having Diagonal Capacitor on Bit Line and a logic device area
Another object of the present invention is to simplify a method of fabricating a semiconductor device by forming the logic device during the formation of the DRAM cell having a structure of Diagonal Capacitor on Bit Line.
Additional features and advantages of the present invention will be set forth in the description which follows, and will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure and process particularly pointed out in the written description as well as in the appended claims.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in accordance with a first aspect of the present invention there is provided a semiconductor device including a semiconductor substrate having an active area including first and second impurity regions of a transistor, a gate formed over the active area of the semiconductor substrate and isolated from the semiconductor substrate, a first insulating interlayer formed on the semiconductor substrate and having first and second contact holes exposing the first and the second impurity regions, respectively, a capacitor having a storage electrode and a plate electrode, the storage electrode being connected electrically to the first impurity region through the first contact hole, a bit line contact pad connected electrically to the second impurity region through the second contact hole, a second insulating interlayer formed on the plate electrode and having a third contact hole exposing the bit line contact pad, and a bit line formed on the second insulating interlayer and in contact with the bit line contact pad through the third contact hole.
In another aspect of the present invention there is provided a semiconductor device including a semiconductor substrate having a diagonal type active area including first and second impurity regions -of a transistor, a gate formed over the active area and isolated from the semiconductor substrate, a first insulating interlayer formed on the semiconductor substrate and having first and second contact holes exposing the first and the second impurity regions, respectively, a capacitor having a hexagonal-shaped storage electrode and a plate electrode, the storage electrode being connected electrically to the first impurity region through the first contact hole, a dielectric film interposed between the plate electrode and the storage electrode, a bit line contact pad connected electrically to the second impurity region through the second contact hole, a second insulating interlayer formed on the plate electrode and having a third contact hole exposing the bit line contact pad, and a bit line formed on the second insulating interlayer and in contact with the bit line contact pad through the third contact hole.
In another aspect of the present invention there is provided a method of fabricating a semiconductor device including the steps of defining an active area on a semiconductor substrate, forming a transistor having a gate and first and second impurity regions on the active area, forming a first insulating interlayer on the semiconductor substrate, forming first and second contact holes exposing the first and the second impurity regions, respectively, forming a storage electrode in the first contact hole and in contact with the first impurity region, and also forming a bit line contact pad in the second contact hole and in contact with the second impurity region, forming a dielectric film on the storage electrode, forming a plate electrode on the dielectric film, forming a second insulating interlayer on the plate electrode and the bit line contact pad, forming a third contact hole in the second insulating interlayer by removing a portion of the second insulating interlayer to expose the bit line contact pad, and forming a bit line on the second insulating interlayer in contact with the bit line contact pad through the third contact hole.
In another aspect of the present invention there is provided a method of fabricating semiconductor device including the steps of defining an active area having a diagonal shape on a semiconductor substrate, forming a transistor having a gate and first and second impurity regions in the active area, forming a first insulating interlayer on the semiconductor substrate, forming first and second contact holes in the first insulating interlayer and exposing the first and second impurity regions, respectively, forming a hexagonal-shaped storage electrode and a bit line contact pad in the first and second contact holes, respectively, and in contact with the first and second impurity regions, respectively, forming a dielectric film on the storage electrode, forming a plate electrode on the dielectric film, forming a second insulating interlayer on the plate electrode and the bit line contact pad, forming a third contact hole by patterning the second insulating interlayer to expose the bit line contact pad, and forming a bit line on the second insulating interlayer in contact with the bit line contact pad through the third contact hole.
In another aspect of the present invention there is provided a semiconductor device including a substrate having an active region, a drain region formed in the active region, a source region formed in the active region, a gate formed over the substrate and isolated from the substrate by an insulating layer, a first insulating interlayer formed over the gate and the insulating layer, a first contact hole formed over the source region, a second contact hole formed over the drain region, a storage electrode formed in contact with the source region in the first contact hole, a bit line contact pad formed in contact with the drain region in the second contact hole, a dielectric film formed over the storage electrode, a plate electrode formed over the dielectric film, a second insulating interlayer formed over the storage electrode, a third contact hole formed in the second insulating interlayer exposing a portion of the bit line contact pad and a bit line formed over the second insulating interlayer and in contact with the bit line contact pad through the third contact hole.
In another aspect of the present invention there is provided a method of fabricating a semiconductor device including the steps of forming an active region in a semiconductor substrate, forming a source region and a drain region in the active region, forming a gate over the active region, wherein the gate is isolated from the semiconductor substrate by an insulating layer, forming a first insulating interlayer over the insulating layer, forming a first contact hole in the insulating layer and the first insulating interlayer to expose the source region, and a second contact hole in the insulating layer and the first insulating interlayer to expose the drain region, forming a storage electrode in contact with the source region and filling the first contact hole, and forming a bit line contact pad in contact with the drain region and filling the second contact hole, forming a dielectric film over the storage electrode, forming a plate electrode over the dielectric film and over the storage electrode, forming a second insulating interlayer covering the plate electrode and at least partly covering the bit line contact pad, forming a third contact hole in the second insulating interlayer, and forming a bit line over the second insulating interlayer and in contact with the bit line contact pad.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.